artale 55d6cd5333 docs(tac): add Memory vs Taste architecture pattern ... Folds the Memory vs Taste concept into loop_engineering.md. Memory is raw storage/retrieval (vector DB, full histories). Taste is higher-order judgment (significance extraction, preferences, lessons). Applied to TAC: skill_health.py as the bridge, deploy policy as taste, 25 containers + qdrant as memory.		2026-07-09 06:48:08 +02:00
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loop_engineering.md	docs(tac): add Memory vs Taste architecture pattern	2026-07-09 06:48:08 +02:00
plan_assumptions.md	feat(tac): add product factory loop hardening	2026-06-29 11:56:54 +02:00